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[assembly language] 111.ver

Description: verilog code for CPU design by Mohammad Hosseini.
Platform: | Size: 2048 | Author: Mohammad | Hits:

[assembly language] 111moh

Description: verilog code for cpu and registers.
Platform: | Size: 2048 | Author: Mohammad | Hits:

[VHDL-FPGA-Verilog] cpu_lynn

Description: Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
Platform: | Size: 11264 | Author: wei | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog HDL编写的一个精简指令的处理器，很好用，可用来学习-Verilog HDL RISC_CPU
Platform: | Size: 14336 | Author: | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code

Description: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Platform: | Size: 79872 | Author: 曾亮 | Hits:

[VHDL-FPGA-Verilog] cpu_16bit

Description: design cpu 16 bits by verilog HDL.
Platform: | Size: 1024 | Author: tommy | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST
Platform: | Size: 328704 | Author: 魏文沫 | Hits:

[VHDL-FPGA-Verilog] alu

Description: mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
Platform: | Size: 4096 | Author: yzhang | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] KD-CPU

Description: 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
Platform: | Size: 503808 | Author: 张鸿云 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
Platform: | Size: 1735680 | Author: era | Hits:

[VHDL-FPGA-Verilog] cpu

Description: cpu design in verilog
Platform: | Size: 275456 | Author: ujjwal | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
Platform: | Size: 19456 | Author: qc | Hits:

[VHDL-FPGA-Verilog] RISC_cpu

Description: 基于RISC结构的8位微处理器的verilog源代码，很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
Platform: | Size: 263168 | Author: 西门吹雪 | Hits:

[VHDL-FPGA-Verilog] cpu-kongzhi

Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation.
Platform: | Size: 1024 | Author: dino | Hits:

[VHDL-FPGA-Verilog] multi-CPU

Description: Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
Platform: | Size: 2049024 | Author: gtx | Hits:
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